1. Field of the Invention
The present invention relates to a semiconductor device, particularly but not limited to a semiconductor device having a MOS transistor and an inductor.
2. Description of the Related Art
An important characteristic of high frequency semiconductor device is to enhance the noise characteristics of the high frequency circuit by reducing noise caused in the substrate. As an inductor occupies a large area, in comparison to other circuit element, high frequency current flows in the substrate by coupling a wiring layer pattern composing the inductor and the substrate immediately under the inductor, thus causing noise in the substrate due to the resistance of the substrate. The noise has a negative effect upon the characteristics of the high frequency circuit To reduce the noise in the substrate, the method of the present invention provides a conductive layer made of a metallic suicide layer placed between an inductor pattern and a silicon substrate thus shielding conductive layer via metallic wire grounding However, as eddy current is caused in the metallic silicide layer a problem occurs wherein that the quality factor Q of the inductor deteriorates.
A conventional solution to the above problem is disclosed on page 85 and 86 of xe2x80x9c1997 Symposium on VLSI Circuits Digest of Technical Papersxe2x80x9d which teaches structuring an inductor for reducing eddy current by providing slitting to a metallic silicide layer. FIG. 1 is a plan view showing an example of the conventional solution. FIG. 2 is a sectional view along a line AA of FIG. 1 Referring to FIGS. 1 and 2, the example of the conventional solution will be described below.
In a semiconductor device 100, an inductor is formed by second-layer metallic wiring 114b of a spiral type inductor pattern. A polysilicon 105b and a metallic silicide 108b thereon is provided under the second-layer metallic wiring 114b with a first layer insulation film 109 and a second layer insulation film 112. The metallic silicide 108b on the surface of the polysilicon 105b is made of metal such as titanium, cobalt and nickel. The metallic silicide 108b is thus located between the second-layer metallic wiring 114b and the polysilicon 105b. Also, concave slitting 115 is provided to the polysilicon 105b directionally inward from the side of the outer edge.
One end of the inductor is connected to the polysilicon 105a, via a through hole 113, first layer metallic wiring 111 and a contact hole 110. The polysilicon 105a is the gate electrode of an N-channel MOS transistor 120. In FIGS. 1 and 2, reference numeral 101 denotes a P-type silicon substrate, 102 denotes an element isolation oxide film, 103 denotes a P-type well, 106 denotes a side wall of an insulating film, 107 denotes N-type source and drain areas, 108c denotes metallic suicide and 114a denotes second-layer metallic wiring.
To clarify the characteristics of the conventional structure, a plan view at the stage at which the metallic silicides 108a, 108b and 108c are formed is shown in FIG. 3. As shown in FIG. 3, hatching sloping leftward and downward is provided for the metallic silicide 108a on the polysilicon 105a of the gate electrode and the metallic silicide 108b on the polysilicon 105b under the inductor pattern in common. Hatching sloping rightward and downward is provided for the metallic silicide 108c formed on the surface of the silicon substrate where the N-type source and drain areas 107 of the N-channel MOS transistor 120.
According to this structure, as the metallic silicide layer 108b on the polysilicon 105b under the inductor pattern is grounded, noise caused in the P-type silicon substrate 101 can be reduced to a considerable extent. Furthermore, as slitting 115 is provided to the polysilicon 105b and the metallic silicide layer 108b respectively under the inductor pattern, eddy current can also be prevented.
However, in this example of the conventional solution, as an area of the slitting 115 of the polysilicon 105b is not shielded, high frequency current cannot be prevented from flowing to the P-type silicon substrate 101 through the area of the slitting 115. This causes a problem of antimony. Thus, as more slittings 115 are provided to complete the inhibition of eddy current, the shielding performance is conversely deteriorated.
An aspect of the invention is to provide a semiconductor device wherein the above-mentioned problem of antinomy is solved. The semiconductor device of the present invention enables the enhancement of the performance of shielding and the inhibition of eddy currant respectively between an inductor and a substrate. Therefore, the noise in the substrate can be reduced and the deterioration of the quality factor Q of the inductor, due to eddy current, can also be inhibited.
In an embodiment of the semiconductor device of the present invention, a semiconductor device wherein a circuit in which an active device including a MOS transistor and an inductor are mixed is mounted on a semiconductor substrate and is provided with a first shield pattern made of a conductive film. The first shield pattern is provided between an inductor and the surface of a semiconductor substrate under the inductor thus insulating the inductor from the surface of the semiconductor substrate by a fist insulating film, is insulated from the inductor by a second insulating film and is provided with plural concave slittings from the side of the edge toward the inside and a second shield pattern provided a convex area which is located on the surface of the semiconductor substrate in registration with the slitting and in which metallic silicide is formed and a connection area which is provided on the surface of the semiconductor substrate and in which metallic silicide is formed for connecting plural convex areas.
In another embodiment of a semiconductor of the present invention, a semiconductor device wherein a circuit in which an active device including a MOS transistor and an inductor arc mixed is mounted on a semiconductor substrate and is provided with a first shield pattern made of metallic silicide which is provided on the surface of a semiconductor substrate under an inductor and is provided with plural concave slittings from the side of the edge toward the inside and a second shield pattern provided between the inductor and the surface of the semiconductor substrate, insulated from the surface of the semiconductor substrate by a first insulating film, insulated from the inductor by a second insulating film and provided with a convex conductive film provided on the surface of the semiconductor substrate in registration with the slitting and a connection area made of the conductive film for connecting the plural convex conductive films